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P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 10/12/15/20/25/35/45/55 ns (Commercial) - 15/20/25/35/45/55 ns (P4C148 Military) Low Power Operation Single 5V 10% Power Supply Two Options - P4C148 Low Power Standby Mode - P4C149 Fast Chip Select Control Common Input/Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) - 18 Pin 300 mil DIP - 18 Pin LCC (295 x 335 mil) [P4C148 only] - 18 Pin LCC (290 x 430 mil)
DESCRIPTION
The P4C148 and P4C149 are 4,096-bit ultra high-speed static RAMs organized as 1K x 4. Both devices have common input/output ports. The P4C148 enters the standby mode when the chip enable (CE) goes HIGH; with CMOS input levels, power consumption is extremely low in this mode. The P4C149 features a fast chip select capability using CS. The CMOS memories require no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V 10% tolerance power supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption when active; for the P4C148, consumption is further reduced in the standby mode. The P4C148 and P4C149 are available in 18-pin 300 mil DIP packages, as well as 2 different LCC packages, providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
P4C148 DIP (C9, D1, P1) P4C149 DIP (P1)
P4C148 LCC (L7, L7-1) P4C149 LCC (L7)
Document # SRAM104 REV B 1 Revised April 2007
P4C148/P4C149
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value - 0.5 to +7 - 0.5 to VCC +0.5 - 55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value - 55 to +125 - 65 to +150 1.0 50 Unit C C W mA
VTERM TA
V C
RECOMMENDED OPERATING CONDITIONS
Grade(2) Commercial Military Ambient Temp 0C to 70C -55C to +125C Gnd 0V 0V VCC 5.0V 10% 5.0V 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF
Output Capacitance VOUT= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2) Sym. VOH VOL VIH VIL ILI ILO ISB ISB1 Parameter Output High Voltage (TTL Load) Output Low Voltage (TTL Load) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC = Max., VIN = GND to VCC VCC = Max., CE, CS = VIH, VOUT = GND to VCC Mil. Comm'l Mil. Comm'l Mil. Comm'l Mil. Comm'l Test Conditions IOH = -4 mA, VCC = Min. IOL = +8 mA, VCC = Min 2.2 -0.5(3) -10 -5 -10 -5 P4C148 Min. 2.4 0.4 VCC+0.5 0.8 +10 +5 +10 +5 30 23 15 10 2.2 -0.5(3) -10 -5 -10 -5 Max. P4C149 Min. 2.4 0.4 VCC+0.5 0.8 +10 +5 +10 +5 N/A N/A N/A N/A Max. Unit V V V V A A mA mA
Standby Power Supply CE VIH, VCC = Max., Current (TTL Input Levels) f=Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE VHC, VCC = Max., f= 0, Outputs Open VIN 0.2V or VIN VCC -0.2V
N/A = Not Applicable
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter ICC Dynamic Operating Current Temperature Range Commercial Military -10 -12 -15 -20 -25 -35 -45 -55 Unit 130 130 120 115 100 100 95 95 mA N/A N/A 145 135 125 120 115 115 mA
Document # SRAM104 REV B
Page 2 of 10
P4C148/P4C149
AC CHARACTERISTICS--READ CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym tRC tAA tAC tAC tOH tLZ tHZ tRCS tRCH tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time (P4C148) Chip Enable Access Time (P4C149) Output Hold from Address Change Chip Enable to Output in Low Z (P4C149) Chip Disable to Output in High Z (P4C149) Read Command Setup Time Read Command Hold Time Chip Enable to Power Up Time (P4C148) Chip Disable to Power Down Time (P4C148) 0 0 0 10 3 2 4 0 0 0 12 -10 -12 -15 -20 -25 -35 -45 -55 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 10 10 8 3 2 5 0 0 0 15 12 12 10 3 2 6 0 0 0 20 15 15 12 3 2 8 0 0 0 25 20 20 14 3 2 10 0 0 0 35 25 25 15 3 2 14 0 0 0 45 35 35 20 3 2 18 0 0 0 55 45 45 20 3 2 20 55 55 25
TIMING WAVEFORM OF READ CYCLE
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and
-100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured 200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM104 REV B
Page 3 of 10
P4C148/P4C149
AC CHARACTERISTICS--WRITE CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym Parameter t WC Write Cycle Time t CW tAW tAS tWP tAH t DW tDH tWZ t OW Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 -10 -12 -15 -20 -25 -35 -45 -55 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 8 8 0 8 0 5 0 5 0 10 10 0 10 0 6 0 6 0 12 12 0 12 0 7 0 7 0 16 16 0 16 0 9 0 7 0 20 20 0 20 0 12 0 8 0 25 25 0 25 0 16 0 12 0 30 30 0 30 0 20 0 15 0 35 35 0 35 0 25 0 20
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9) WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CS CONTROLLED)(9) CE/CS CE
Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address.
Document # SRAM104 REV B
Page 4 of 10
P4C148/P4C149
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
TRUTH TABLE
Mode Standby Read Write CE H L L WE X H L Output High Z DOUT High Z Power Standby Active Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note: Due to the ultra-high speed of the P4C148/149, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency
capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance).
Document # SRAM104 REV B
Page 5 of 10
P4C148/P4C149
ORDERING INFORMATION
SELECTION GUIDE
The P4C148/P4C149 are available in the following temperature, speed and package options.
Temperature Range Commercial Temperature Military Temperature Package Plastic DIP Side Brazed DIP CERDIP Side Brazed DIP LCC (290 x 430 mil) LCC (295 x 335 mil) CERDIP Military Processed* Side Brazed DIP LCC (290 x 430 mil) LCC (295 x 335 mil) Speed (ns) 10 -10PC -10CC N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC -12CC N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15CC -15DM -15CM -15LM -15LSM -15DMB -15CMB -15LMB -15LSMB 20 -20PC -20CC -20DM -20CM -20LM -20LSM -20DMB -20CMB -20LMB -20LSMB 25 -25PC -25CC -25DM -25CM -25LM -25LSM -25DMB -25CMB -25LMB -25LSMB 35 -35PC -35CC -35DM -35CM -35LM -35LSM -35DMB -35CMB -35LMB -35LSMB 45 -45PC -45CC -45DM -45CM -45LM -45LSM -45DMB -45CMB -45LMB 55 -55PC -55CC -55DM -55CM -55LM -55LSM -55DMB -55CMB -55LMB
-45LSMB -55LSMB
* Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available
Document # SRAM104 REV B
Page 6 of 10
P4C148/P4C149
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C9
18 (300 Mil) Min Max 0.200 0.014 0.026 0.030 0.065 0.008 0.018 0.960 0.220 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 -
SIDE BRAZED DUAL IN-LINE PACKAGES
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1
D1
18 (300 Mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 0.960 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0 15
CERDIP DUAL IN-LINE PACKAGES
Document # SRAM104 REV B
Page 7 of 10
P4C148/P4C149
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L7
18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.417 0.440 0.200 BSC 0.100 BSC 0.440 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.075 0.090 0.075 0.148 4 5
RECTANGULAR LEADLESS CHIP CARRIER
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L7-1
18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.345 0.365 0.200 BSC 0.100 BSC 0.365 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.125 4 5
RECTANGULAR LEADLESS CHIP CARRIER (SMALL)
Document # SRAM104 REV B
Page 8 of 10
P4C148/P4C149
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P1
18 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 0.880 0.920 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE
Document # SRAM104 REV B
Page 9 of 10
P4C148/P4C149
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B ISSUE DATE 1997 Oct-05 Apr-07 SRAM104
P4C148/P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS
ORIG. OF CHANGE DAB JDB JDB
DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added 45 and 55 ns speeds
Document # SRAM104 REV B
Page 10 of 10

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